altera小实验——HEX 7-segment display

实验所用板子为altera DE2板子，FPGA为Cyclone II:EP2C35F672C6，quartus版本为13.0

实验目的

在DE2板子的7-segment display数字显示屏HEX0上每秒加一显示数字0-9。

KEY[0]为复位信号，按下时为0。

实验代码

/*HEX0[0] = 1'b0; //enable |||||[0]||||[5]      [1]|||      ||||||||[6]||||[4]      [2]|||      ||||||||[3]||||*/module work	#(		parameter ZERO 	= 7'b1000000,		parameter ONE 	= 7'b1111001,		parameter TWO 	= 7'b0100100,		parameter THREE = 7'b0110000,		parameter FOUR 	= 7'b0011001,		parameter FIVE 	= 7'b0010010,		parameter SIX 	= 7'b0000010,		parameter SEVEN = 7'b1111000,		parameter EIGHT = 7'b0000000,		parameter NINE  = 7'b0010000		) 	(	CLOCK_50,	KEY,	HEX0		);input CLOCK_50;input [3:0]KEY;output [6:0]HEX20;wire rst = !KEY[0];wire clk = CLOCK_50;reg [7:0]NUMBER [9:0];always @(posedge clk or posedge rst) begin	if (rst) begin		NUMBER[0] <= ZERO;		NUMBER[1] <= ONE;		NUMBER[2] <= TWO;		NUMBER[3] <= THREE;		NUMBER[4] <= FOUR;		NUMBER[5] <= FIVE;		NUMBER[6] <= SIX;		NUMBER[7] <= SEVEN;		NUMBER[8] <= EIGHT;		NUMBER[9] <= NINE;	end	else begin		NUMBER[0] <= NUMBER[0];		NUMBER[1] <= NUMBER[1];		NUMBER[2] <= NUMBER[2];		NUMBER[3] <= NUMBER[3];		NUMBER[4] <= NUMBER[4];		NUMBER[5] <= NUMBER[5];		NUMBER[6] <= NUMBER[6];		NUMBER[7] <= NUMBER[7];		NUMBER[8] <= NUMBER[8];		NUMBER[9] <= NUMBER[9];	endendreg [27:0]cnt; //手动分频reg clk_1Hz;   //50M -> 1Hzalways @(posedge clk or posedge rst) begin	if (rst) begin		// reset		cnt <= 28'b0;	end	else if (cnt == 28'd24999999) begin		cnt <= 28'b0;	end	else begin		cnt <= cnt + 1'b1;	endendalways @(posedge clk or posedge rst) begin	if (rst) begin		// reset		clk_1Hz <= 1'b0;	end	else if (cnt == 28'd24999999) begin		clk_1Hz <= ~clk_1Hz;	end	else begin		clk_1Hz <= clk_1Hz;	endendreg [3:0]light;always @(posedge clk_1Hz or posedge rst) begin	if (rst) begin		// reset		light <= 4'b0;	end	else if (light == 4'd9) begin		light <= 4'b0;	end	else begin		light <= light + 1'b1;	endendassign HEX0 = NUMBER[light];endmodule